computer science//real-time computing//periodic task

A periodic task is a unit of work that a real-time system releases at a fixed rate and must finish before a deadline, described by four numbers, and it is the model with which engineers check that an autopilot or a PLC program will meet all its deadlines before it flies or runs. Almost every embedded control loop is one: read the sensors, estimate, compute the command, write the actuators, wait for the next tick.

A periodic task is a unit of work that a real-time system releases at a fixed rate and must finish before a deadline, described by four numbers, and it is the model with which engineers check that an autopilot or a PLC program will meet all its deadlines before it flies or runs. Almost every embedded control loop is one: read the sensors, estimate, compute the command, write the actuators, wait for the next tick.

The four numbers are the period TTT (how often it is released), the deadline DDD (the latest acceptable completion, usually equal to the period), the worst-case execution time CCC (the longest one release can take) and its jitter (how much its start or finish wanders). The ratio C/TC/TC/T is the fraction of the processor the task needs, and summing it over all tasks gives the utilization that real-time scheduling works with. An attitude task with T=2T=2T=2 ms and C=0.12C=0.12C=0.12 ms uses 6 % of the CPU; an EKF with T=10T=10T=10 ms and C=0.8C=0.8C=0.8 ms uses 8 %.

The fixed-rate control loop is the skeleton behind all of this, written the same way on a drone and in a plant:

1Wait for the timer tick2Read the sensors3Estimate the state4Compute the command5Write the actuators6Check the deadlinewhat if it was missed?

The period is chosen from the dynamics: sample 10 to 30 times faster than the closed-loop bandwidth you want (sampling rate selection), because sampling and computation add about half a period of delay each.

The loop is a timer-driven control loop: a hardware timer releases it, never a software sleep, whose wake-up time inherits every delay of the scheduler and turns into jitter in the derivative.

The last step asks the question most prototypes skip: what happens when a release overruns? The choices are to skip the next cycle, to run late and catch up, or to fall back to a safe action (fail-safe design), and each must be chosen on purpose.

The PLC scan cycle is the same model with one task: read inputs, execute, write outputs, bounded in time.