hardware//chip//FPGA

An **FPGA** (field-programmable gate array) is a chip whose logic and connections can be configured after it has been manufactured. It does more than run a program over a fixed datapath: it rearranges logic blocks, registers, memories and interconnect routes so that the chip itself takes the shape of the circuit required. A CPU is configured with a sequence of instructions over general hardware, and a GPU offers massive parallelism over a fixed architecture; an FPGA configures part of the datapath itself, so a specific parallel architecture can be built for one workload. It is especially useful in signal and packet processing, video, high-speed interfaces, inference with custom precision and systems that need deterministic latency.

An FPGA (field-programmable gate array) is a chip whose logic and connections can be configured after it has been manufactured. It does more than run a program over a fixed datapath: it rearranges logic blocks, registers, memories and interconnect routes so that the chip itself takes the shape of the circuit required. A CPU is configured with a sequence of instructions over general hardware, and a GPU offers massive parallelism over a fixed architecture; an FPGA configures part of the datapath itself, so a specific parallel architecture can be built for one workload. It is especially useful in signal and packet processing, video, high-speed interfaces, inference with custom precision and systems that need deterministic latency.

The configurable fabric combines LUTs (small tables that implement logic functions), flip-flops, RAM blocks, DSP units, I/O pins and a programmable routing network. In many FPGAs, millions of SRAM bits determine what each LUT holds and which inputs are selected by the multiplexers, switch boxes and pass transistors that connect one block to another.

A logical connection does not usually correspond to a dedicated wire. The signal can cross several configurable segments and switches.

The configuration SRAM describes the active circuit; it does not normally store the workload's data. Because SRAM is volatile, many FPGAs load a bitstream from external memory at boot, while other families use flash or antifuse.

Changing the bitstream reuses the same chip to represent another circuit without fabricating new silicon.

Configurability has a physical cost. The SRAM, the multiplexers, the switches and the general routing need more transistors, area and energy for the same logic function, and every switch and routing segment adds resistance and capacitance to the signal's path. A function on an FPGA usually runs at a lower frequency and efficiency than its equivalent in an ASIC, which freezes a specialized datapath in silicon and drops the reconfigurable infrastructure; the FPGA pays that overhead in every unit to avoid the huge upfront cost of designing and fabricating another chip.

An FPGA can lay out an algorithm's operations in different regions of the hardware and make the data flow physically from one stage to the next. While stage 3 processes datum A, stage 2 processes B and stage 1 receives C; once the pipeline is full it can finish one result per cycle, even though each datum takes several cycles to cross it. This avoids constantly reusing a single machinery through fetch, decode and execute, as a general-purpose CPU does. Time partly becomes space: operations and stages are replicated to run simultaneously.

Memory does not disappear. Registers, FIFOs, block RAM and buffers keep the state between stages and absorb differences in pace; what can shrink is part of the load/store traffic and of the general control machinery. It works best on regular streams, and can lose to a CPU or a GPU when the workload changes continuously, depends on irregular memory or does not produce enough flow to keep the pipeline busy.

In a control system it serves the loops faster or more parallel than a microcontroller can handle. Configured as a circuit, it performs hundreds of multiplications per cycle with a latency of nanoseconds that never varies, so it closes the current loops of motor drives, processes radar returns and preprocesses images ahead of a processor. The price is development (hardware description languages, synthesis runs of hours, debugging with an oscilloscope), which is why it is chosen only when an MCU cannot meet the deadline (embedded system).

The useful picture is a configurable channel. A CPU passes different operations through a general machinery; an FPGA rearranges part of the machinery so that many data cross the same circuit in a continuous flow.