hardware//manufacturing//advanced packaging

Advanced packaging is the set of techniques that place several chips, such as a logic die and stacks of memory, side by side or on top of each other with dense interconnections between them, and it is what turns separate dies into a single AI accelerator. An ordinary package connects one die to a circuit board through relatively few, coarse contacts; an AI accelerator needs thousands of fine wires between its processor and its HBM stacks.

Advanced packaging is the set of techniques that place several chips, such as a logic die and stacks of memory, side by side or on top of each other with dense interconnections between them, and it is what turns separate dies into a single AI accelerator. An ordinary package connects one die to a circuit board through relatively few, coarse contacts; an AI accelerator needs thousands of fine wires between its processor and its HBM stacks.

The dominant form for AI chips is TSMC's CoWoS (chip on wafer on substrate): the dies sit on a thin slice of silicon, the interposer, which carries the fine wiring between them, and the interposer sits on a conventional substrate. Because the interposer is made with chip-making tools, packaging capacity grows on the timescale of a fab, in years.

Packaging became a bottleneck of its own. Through 2025 and 2026 the four largest AI chip designers used most of the world's CoWoS capacity while using only a small share of advanced logic wafers, so the number of accelerators that could be built was set by packaging and memory before wafers.

Newer approaches stack dies vertically (3D integration) or split a processor into chiplets, which moves more of the system into the package.